Field of Invention
Various embodiments of the present disclosure relate generally to semiconductor technology, and more particularly to a voltage generation circuit having an overvoltage prevention feature for a memory device.
Description of Related Arts
Memory devices may include a memory cell array for storing data, a peripheral circuit suitable for performing programming (also referred to as writing operation), reading and erasing operations on the memory cell array, and a control circuit suitable for controlling the peripheral circuit.
The peripheral circuit includes a voltage generation circuit to generate one or more operation voltages for performing the various memory operations.
General, a typical voltage generation circuit may include code tables employed to generate different level operation voltages. For example, a main code table may be used to generate a main voltage, and another table commonly referred to as a trimming code table may be used to trim the main voltage.
A trimming code table may include a variety of codes used to compensate for variations of the main voltage. An abnormal code may be generated from the voltage generation circuit when an operation voltage is outside of an available voltage range. In such a case, the voltage generation circuit may generate an overvoltage as the operation voltage, subjecting the generation circuit, the peripheral circuit and the memory cell array to increased stress. Repeated increased stresses due to overvoltage may degrade the performance of a memory device and associated system.